afct-5815xz 155 mb/s single mode fiber optic transceiver for atm, sonet oc-3/sdh stm-1 data sheet description general the afct?5815xz transceiver is a high performance, cost efective module for serial optical data communications applications specifed for a data rate of 155 mb/s. it is designed to provide a sonet/sdh compliant link for long reach links operating at +3.3 v or +5.0 v input voltage. transmitter section the transmitter section of the afct?5815xz consists of a 1300 nm ingaasp laser in an eyesafe optical subassembly (osa) which mates to the fber cable. the laser osa is driven by a custom ic which converts diferential input pecl logic signals, ecl referenced (shifted) to +3.3 v or +5 v supply, into an analog laser drive current. receiver section the receiver utilizes an ingaas pin photodiode mounted together with a transimpedance preamplifer ic in an osa. this osa is connected to a circuit providing post? amplif ? cation quantization, and optical signal detection. features ? rohs compliant ? long reach sonet oc ? 3 sdh stm1 (l1.1) compliant ? multisourced 1 x 9 pin confguration ? interchangeable with led multisourced 1 x 9 trans ? ceivers ? unconditionally eyesafe laser iec 825/cdrh class 1 compliant ? two temperature ranges: 0c to +70c afct ?5815bz/dz ? 40c to +85c afct ?5815az/cz ? single +3.3 v or +5.0 v power supply operation ? wave solder and aqueous wash process compatible ? considerable emi margin to fcc class b applications ? atm 155 mb/s links for lan backbone switches and routers ? atm 155 mb/s links for wan core, edge and access switches and routers ? atm 155 mb/s links for add/drop multiplexers and demultiplexers ? sonet oc?3/sdh stm?1 interconnections
2 figure 2. relative input optical power - dbm. avg. figure 1. block diagram e l e c t r i c a l s u b a s s e m b l y d a t a s i g n a l d e t e c t d a t a p o s t a m p l i f i e r i c l a s e r d r i v e r i c p r e - a m p l i f i e r i c l a s e r p i n p h o t o d i o d e d u p l e x s c r e c e p t a c l e t o p v i e w o p t i c a l s u b - a s s e m b l i e s d a t a d a t a 1 0 - 2 1 0 - 3 1 0 - 4 1 0 - 5 1 0 - 6 1 0 - 7 1 0 - 8 1 0 - 9 1 0 - 1 0 1 0 - 1 1 1 0 - 1 2 1 0 - 1 3 1 0 - 1 4 1 0 - 1 5 - 5 - 4 - 3 - 2 - 1 0 1 2 3 l i n e a r e x tr a p o l a ti o n o f 1 0 - 4 thr o u g h 1 0 - 7 d a ta b a s e d o n a c tu a l d a ta b i t e r r o r r a t i o applications information typical ber performance of receiver versus input opti - cal power level the afct?5815xz transceiver can be operated at bit?error?rate conditions other than the required ber = 1 x 10 ?10 of the atm forum 155.52 mb/s physical layer standard. the typical trade?of of ber versus relative in ? put optical power is shown in figure 2. the relative input optical power in db is referenced to the actual sensitivity of the device. for ber conditions better than 1 x 10 ?10 , more input signal is needed (+db). receiver signal detect signal detect is a basic fber failure indicator. this is a single?ended pecl output. as the input optical power is decreased, signal detect will switch from high to low (deassert point) somewhere between sensitivity and the no light input level. as the input optical power is increased from very low levels, signal detect will switch back from low to high (assert point). the assert level will be at least 0.5 db higher than the deassert level. transceiver specifed for wide temperature range op - eration the afct?5815xz is specifed for operation over extended temperature range of ?40 to +85c. characterization of the parts has been performed over the ambient operating temperature range in an airfow of 2 m/s. other members of avago technologies sc duplex 155 mb/s product family ? hfct?5801, 1300 nm single mode transceiver for links up to 15 km. the part is based on the 2 x 9 industry standard package and has laser bias, optical power monitor and transmitter disable functions.
3 figure 3. recommended circuit schematic n o i n t e r n a l c o n n e c t i o n n o i n t e r n a l c o n n e c t i o n t o p v i e w r x v e er 1 r d 2 s d 4 r x v ccr 5 t x v cct 6 t d 8 t x v eet 9 t e r m i n a t e a t p h y d e v i c e i n p u t s v c c f i l t e r a t v c c p i n s t r a n s c e i v e r v cc c 2 c 1 l 1 l 2 t d r d 3 t d 7 r 8 r d r d v cc r 5 r 7 r 6 c 6 s d r 1 0 c 7 c 8 c 3 c 4 r 4 v cc r 2 r 3 r 1 t e r m i n a t i o n a t t r a n s c e i v e r i n p u t s t d c 5 r 9 recommended circuit schematic in order to ensure proper functionality of the afct?5815xz a recommended circuit is provided in figure 3. when de ? signing the circuit interface, there are a few fundamental guidelines to follow. for example, in the recommended circuit schematic fgure the diferential data lines should be treated as 50 ohm microstrip or stripline transmission lines. this will help to minimize the parasitic inductance and capacitance efects. proper termination of the dif ? ferential data signals will prevent refections and ringing which would compromise the signal fdelity and gener ? ate unwanted electrical noise. locate termination at the received signal end of the transmission line. the length of these lines should be kept short and of equal length. for the high speed signal lines, diferential signals should be used, not single?ended signals, and these diferential signals need to be loaded symmetrically to prevent un ? balanced currents from fowing which will cause distor ? tion in the signal. maintain a solid, low inductance ground plane for re ? turning signal currents to the power supply. multilayer plane printed circuit board is best for distribution of v cc , returning ground currents, forming transmission lines and shielding, also, it is important to suppress noise from infuencing the fber?optic transceiver performance, especially the receiver circuit. proper power supply fltering of v cc for this transceiver is accomplished by using the recommended, separate flter circuits shown in figure 3 for the transmitter and receiver sections. these flter circuits suppress v cc noise over a broad frequency range, this prevents receiver sensitivity degradation due to v cc noise. it is recommended that surface?mount components be used. use tantalum capacitors for the 10 f capacitors and monolithic, ceramic bypass capaci ? tors for the 0.1 f capacitors. also, it is recommended that a surface? mount coil inductor of 3.3 h be used. ferrite beads can be used to replace the coil inductors when using quieter v cc supplies, but a coil inductor is recommended over a ferrite bead. all power supply components need to be placed physically next to the v cc pins of the receiver and transmitter. use a good, uni ? form ground plane with a minimum number of holes to provide a low ? inductance ground current return for the power supply currents. in addition to these recommendations, avago tech ? nologies application engineering staf is available for consulting on best layout practices with various vendors mux/demux, clock generator and clock recovery circuits. avago technologies has participated in several reference design studies and is prepared to share the fndings of these studies with interested customers. contact your local avago technologies sales representative to arrange for this service. notes: the split ? load terminations for pecl signals need to be located at the input of devices receiving those pecl signals. recommend 4 ? layer printed circuit board with 50 ? microstrip signal paths be used. for +5.0v and +3.3v operation. r1 = r4 = r6 = r8 = r10 = 130 ? r2 = r3 = r5 = r7 = r9 = 82 ? c1 = c2 = 10 f c3 = c4 = c7 = c8 = 100 nf c5 = c6 = 0.1 f l1 = l2 = 3.3 h coil or ferrite inductor.
4 recommended solder fluxes and cleaning/degreasing chemicals solder fuxes used with the afct?5815xz fber?optic transceiver should be water?soluble, organic solder fux ? es. some recommended solder fuxes are lonco 3355?11 from london chemical west, inc. of burbank, ca, and 100 flux from alpha metals of jersey city, nj. recommended cleaning and degreasing chemicals for the afct?5815xz are alcohols (methyl, isopropyl, isobu ? tyl), aliphatics (hexane, heptane) and other chemicals, such as soap solution or naphtha. do not use partially halogenated hydrocarbons for cleaning/degreasing. ex ? amples of chemicals to avoid are 1.1.1. trichloroethane, ketones (such as mek), acetone, chloroform, ethyl ac ? etate, methylene dichloride, phenol, methylene chloride or n? methylpyrrolidone. evaluation circuit boards evaluation circuit boards are available from avago tech ? nologies application engineering staf. contact your local avago technologies sales representative to arrange for access to one if needed. recommended solder and wash process the afct?5815xz is compatible with industry standard wave or hand solder processes. a drying cycle must be completed after wash process to remove all moisture from the module. afct - 5815xz process plug the afct?5815xz transceiver is supplied with a process plug for protection of the optical ports with the duplex sc connector receptacle. this process plug prevents con ? tamination during wave solder and aqueous rinse as well as during handling, shipping or storage. each process plug can only be used once during processing, although with subsequent use, it can be used as a dust cover. it is made of high?temperature, molded, sealing material that will withstand +85c and a rinse pressure of 110 lb/in 2 . figure 4. recommended board layout hole pattern 20.32 (0.800) to p v ie w 2 x ? 1.9 0.1 (0.075 0.004) 20.32 (0.800) 2.54 (0.100) 9 x ? 0.8 0.1 (0.032 0.004) d ime n s io n s a re in mil l ime te rs (in c h e s )
5 figure 5. package outline drawing and pinout m ax . +0 .1 -0 .0 5 +0 .0 0 4 -0 .0 0 2 0 .2 5 ( 0 .0 1 0 3 .3 0 .3 8 ( 0 .1 3 0 0 .0 1 5 ) 9 .8 ( 0 .3 8 6 ) 0 .5 1 ( 0 .0 2 0 ) ) 8 x ) 9 x ? 2 x ? ) 2 x ? +0 .2 5 -0 .0 5 +0 .0 1 0 -0 .0 0 2 0 .4 6 ( 0 .0 1 8 2 3 .8 ( 0 .9 3 7 ) 2 0 .3 2 ( 0 .8 0 0 ) 2 .5 4 ( 0 .1 0 0 ) 1 .3 ( 0 .0 5 1 ) 2 0 .3 2 0 .2 ( 0 .8 0 0 0 .0 0 8) 2 0 .3 2 0 .2 ( 0 .8 0 0 0 .0 0 8) 1 5 .8 0 .1 5 ( 0 .6 2 2 0 .0 0 6 ) +0 .2 5 -0 .0 5 +0 .0 1 0 -0 .0 0 2 1 .2 7 ( 0 .0 5 0 d i m e n s i o n s ar e i n m i l l i m e te r s ( i n ch e s ) . to l e r an ce s : 0 .1 mm u n l e s s o th e r w i s e s p e ci f i e d . k e y: yyw w = d a te c o d e x x x x - x x x x = af c t- 5815 z z z z = 1300 n m 3 9 .6 ( 1 .5 6 ) m ax . m ax . s l o t d e p th x x x x - x x x x z z z z z l a s e r pro d 21c f r(j) c l a s s 1 c o u n try o f o rig in yyw w tx rx s l o t w i d th 1 2 .7 ( 0 .5 0 ) 2 5 .4 ( 1 .0 0 ) 2 .5 ( 0 .1 0 ) 2 .0 0 .1 ( 0 .0 7 9 0 .0 0 4 ) 1 2 .7 0 .3 ( 0 .5 0 0 .0 12) ar e a r e s e r ve d f o r p r o ce s s p l u g avago
6 electromagnetic interference (emi) most equipment designs utilizing these high?speed transceivers from avago technologies will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. the afct?5815xz has been characterized without a chas ? sis enclosure to demonstrate the robustness of the parts integral shielding. performance of a system containing these transceivers within a well designed chassis is ex ? pected to be better than the results of these tests with no chassis enclosure. immunity equipment utilizing these afct?5815xz transceivers will be subject to radio?frequency electromagnetic felds in some environments. these transceivers, with their inte ? gral shields, have been characterized without the beneft of a normal equipment chassis enclosure and the results are reported below. performance of a system contain ? ing these transceivers within a well designed chassis is expected to be better than the results of these tests without a chassis enclosure. regulatory compliance the afct?5815xz is intended to enable commercial system designers to develop equipment that complies with the various regulations governing certifcation of information technology equipment. see the regulatory compliance table 1 for details. additional information is available from your avago technologies sales repre ? sentative. electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the frst case is during handling of the transceiver prior to mounting it on the circuit board. it is important to use normal esd handling precautions for esd sensitive devices. these precautions include using grounded wrist straps, work benches and foor mats in esd controlled areas. the second case to consider is static discharges to the exterior of the equipment chassis containing the trans ? ceiver parts. to the extent that the duplex sc connector is exposed to the outside of the equipment chassis it may be subject to whatever esd system level test criteria that the equipment is intended to meet.
7 table 1. regulatory compliance - typical performance feature test method performance electrostatic discharge (esd) to the electrical pins mii?std ?883f method 3015.7 class 1 (>500 v) ? human body model electrostatic discharge (esd) to the duplex sc receptacle variation of iec 61000 ?4?2 air discharge 15 kv electromagnetic interference (emi) fcc class b typically provide greater than 11 db margin below 1 ghz to fcc class b when tested in a gtem with the transceiver mounted to a circuit card without a chassis enclosure at frequencies up to 1 ghz. margins above 1 ghz dependent on customer board and chassis designs. immunity variation of iec 801 ?3 typically show no measurable efect from a 10 v/m feld swept from 27 mhz to 1 ghz applied to the transceiver without a chassis enclosure. eye safety fda cdrh 21 ? cfr 1040 class 1 accession number: 9521220 ?135 iec 60825 ? 1 tuv approved component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equip ? ment including electrical ul file#: e173874 performance specifcations absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. it should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. exposure to the absolute maximum ratings for extended periods can adversely afect device reliability. parameter symbol minimum maximum units notes storage temperature t s ?40 +85 c lead soldering temperature/time ? ? +260/10 c/s input voltage ? gnd v cc v power supply voltage ? 0 6 v operating environment parameter symbol minimum maximum units notes power supply voltage v cc +3.1 +5.25 v ambient operating temperature ? afct ?5815az/cz t op ?40 +85 c 1 ambient operating temperature ? afct ?5815bz/dz t op 0 +70 c 1
8 transmitter section (ambient operating temperature, v cc = 3.1 v to 5.25 v) parameter symbol minimum typical maximum units notes output center wavelength lce 1261 ? 1360 output spectral width (rms) dl ? ? 4.0 nm average optical output power p o ?5 ? 0 dbm 2 extinction ratio e r 10 ? ? db power supply current i cc ? 50 140 ma 3 output eye compliant with telcordia tr ? nwt ? 000253 and itu recommendation g.957 optical rise time t r ? ? 2 ns 4 optical fall time t f ? ? 2 ns 4 data input current ? low i il ?350 ? ? a data input current ? high i ih ? ? 350 a data input voltage ? low v il ? v cc ?2.0 ? ?1.475 v 5 data input voltage ? high v ih ? v cc ?1.165 ? ?0.74 v 5 notes: 1. 2 m/s air fow required. 2. output power is power coupled into a single mode fber. 3. the power supply current varies with temperature. maximum current is specifed at v cc = maximum @ maximum temperature (not including terminations) and end of life. typical power supply current at +25c and +3.3 v or +5.0 v supply. 4. 10% ? 90% values. maximum t r , t f times tested against eye mask. 5. these inputs are compatible with 10 k, 10 kh and 100 k pecl outputs. receiver section (ambient operating temperature, v cc = 3.1 v to 5.25 v) parameter symbol minimum typical maximum units notes receiver sensitivity ? ? ? ?34 dbm 6 maximum input power ? ?7 ? ? dbm 6 power supply current i cc ? 55 100 ma 7 signal detect ? deasserted ? ?45 ? ?34 dbm signal detect ? hysteresis ? 0.5 ? 4 db signal detect assert time (of to on) as_max ? ? 100 s signal detect deassert time (on to of ) ans_max ? ? 350 s signal detect output voltage ? low v ol ? v cc ?1.92 ? ?1.45 v 8 signal detect output voltage ? high v oh ? v cc ?1.1 ? ?0.85 v 8 data output voltage ? low v ol ? v cc ?2.0 ? ?1.45 v 8 data output voltage ? high v oh ? v cc ?1.1 ? ?0.85 v 8 data output rise time t r ? ? 2.2 ns 9 data output fall time t f ? ? 2.2 ns 9 notes 6. sensitivity and maximum input power levels for a 2 23 ?1 prbs with 72 ones and 72 zeros inserted. (itu recommendation g.958). 7. the current includes capacitively coupled 50 ohm terminations. 8. these outputs are compatible with 10 k, 10 kh and 100 k pecl outputs. 9. 20 ? 80% levels.
9 table 2. pin out table pin symbol functional description mounting studs the mounting studs are provided for transceiver mechanical attachment to the circuit board. they are embedded in the housing and are not connected to the transceiver internal circuit. they should be soldered into plated ? through holes on the printed circuit board. 1 v eer receiver signal ground directly connect this pin to receiver signal ground plane. 2 rd+ receiver data out terminate this high ? speed, diferential, pecl output with standard pecl techniques at the follow ? on device input pin. 3 rd ? receiver data out bar terminate this high ? speed, diferential, pecl output with standard pecl techniques at the follow ? on device input pin. 4 sd signal detect normal input optical levels to the receiver result in a logic 1 output.low input optical levels to the receiver result in a fault indication shown by a logic 0 output. signal detect is a single ? ended, pecl output. this output will operate with 270 ? termination resistor to v ee to achieve pecl output levels. this signal detect output can be used to drive a pecl input on an upstream circuit, such as, signal detect input and loss of signal ? bar input. 5 v ccr receiver power supply provide +3.3 or +5.0 v dc via the recommended receiver power supply flter circuit.locate the power supply flter circuit as close as possible to the v ccr pin. 6 v cct transmitter power supply provide +3.3 or +5.0 v dc via the recommended transmitter power supply flter circuit.locate the power supply flter circuit as close as possible to the v cct pin. 7 td ? transmitter data in bar terminate this high ? speed, diferential transmitter data input with standard pecl techniques at the transmitter input pin. 8 td+ transmitter data in terminate this high ? speed, diferential transmitter data input with standard pecl techniques at the transmitter input pin. 9 v eet transmitter signal ground directly connect this pin to the transmitter signal ground plane.
class 1 laser product: this product conforms to the applicable requirements of 21 cfr 1040 at the date of manufacture date of manufacture: avago technologies inc., no 1 yishun ave 7, singapore handling precautions 1. the afct ? 5818xz can be damaged by current surges or overvoltage. power supply transient precautions should be taken. 2. normal handling precautions for electrostatic sensitive devices should be taken. order information: temperature range 0c to +70c afct ?5815bz black case afct ?5815dz blue case temperature range -40c to +85c afct ?5815az black case afct ?5815cz blue case for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2014 avago technologies. all rights reserved. obsoletes av01-0035en av02-2960en - december 9, 2014
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